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Old July 4th, 2011, 20:15   #561
tronix286
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I propose to introduse another very useful commands, that's allows access to the flags register:
Code:
C4 00 00 00	PUSHF 			Store flags register on stack. Increase SP by 2.
C5 00 00 00	POPF			Decrease SP by 2. Load flags register from stack.
Thus, we can load all flags in any register:

Code:
pushf
pop r0

Last edited by tronix286; July 4th, 2011 at 20:21..
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Old July 4th, 2011, 22:19   #562
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Quote:
Originally Posted by LoRd_SnOw View Post
I'm not sure what you mean by that but no i didn't hire ninjas to steal code from Shendo's emulator, i can prove that to you in a PM if you like.

i just think the issues i'm having is just really odd. For instance, some of the fonts are all scrambled, invisible or mixed with different colors. Other times in Hurdle, when i try to reach the door, i hit something invisible and it counts as a hit (not really sure why).
Hey, I didn't say you stole anything!

About your issues: I would check your STM/LDM opcodes, as well as your ANDs and DRW (reg version), as they are all relevant to text-displaying routines (maybe use a testrom). Check the source code for Herdle if you want.

Hitting something invisible in Herdle: either you are hitting a sheep that wasn't drawn, the collision map is corrupted, or you are simply running out of "PATH" (bottom right of screen). Happy debugging!

Quote:
Originally Posted by tronix286 View Post
I propose to introduse another very useful commands, that's allows access to the flags register:
Code:
C4 00 00 00	PUSHF 			Store flags register on stack. Increase SP by 2.
C5 00 00 00	POPF			Decrease SP by 2. Load flags register from stack.
Thus, we can load all flags in any register:

Code:
pushf
pop r0
Why not, although on a simple system like Chip16 it may not be absolutely necessary. Do you have any strong examples of how that could be used? (I think of multi-tasking OS... )
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Old July 4th, 2011, 22:20   #563
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Quote:
Originally Posted by BestCoder View Post
@cottonvibes do you know why the fliptest doesn't run infinitely in you emu?

EDIT: @cottonvibes , it seems that you have a happy debugging with opcodes C3 and C2.
thanks for the info. i have fixed both the problems.
the fliptest problem was that i wasn't initializing the stack pointer.
and i had a bug in popall where i popped the registers in the reverse order

here's the link to my updated emulator:
http://forums.ngemu.com/1975522-post516.html
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Old July 4th, 2011, 22:52   #564
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Quote:
Originally Posted by tronix286 View Post
I think we need command to load user-define pallete. Somethink like this:

Code:
03 FF LL HH	PAL HHLL        	Load user-defined pallete from address HHLL. If HHLL = 0, load standart chip-16 pallete.
Where pallete is array of 48-bytes (16*3) RGB values. When PAL command done, screen redrawn with new pallete. This will make such effects as: fade-in, fade-out and more..
What do you think?
a palette instruction would be interesting although depending on how it works it can complicate things.

the easiest way for it to work from an emulation point of view would be that once the palette is set, the next time the screen is drawn it uses that new palette.
i.e. every frame can only use at-most 15 different colors (and the transparent 0 color).

the hard implementation would be that you can have multiple palette changes per frame, and can draw different sprites using different palettes. i advise we don't do it this way because its more complex and makes emulation slower.

also the opcode for the instruction should probably be a different byte so that its simpler to implement the opcode switch table.
i.e.
Code:
D0 00 LL HH	PAL HHLL        	Load user-defined palette from address HHLL. If HHLL = 0, load standard chip-16 palette.
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Old July 4th, 2011, 22:55   #565
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Quote:
Originally Posted by tronix286 View Post
I propose to introduse another very useful commands, that's allows access to the flags register:
Code:
C4 00 00 00	PUSHF 			Store flags register on stack. Increase SP by 2.
C5 00 00 00	POPF			Decrease SP by 2. Load flags register from stack.
Thus, we can load all flags in any register:

Code:
pushf
pop r0

i was going to add that but when i thought about it, i didn't find much use for having those instructions so i left it out of the spec.
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Old July 5th, 2011, 06:25   #566
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Quote:
Originally Posted by tykel View Post
Why not, although on a simple system like Chip16 it may not be absolutely necessary. Do you have any strong examples of how that could be used? (I think of multi-tasking OS... )
Quote:
Originally Posted by cottonvibes
i was going to add that but when i thought about it, i didn't find much use for having those instructions so i left it out of the spec.
It's needed for my pascal compiler. I used carry and zero flags in hard conditionals, such as:
Code:
IF (a>b) and (c<e) or (d=a) THEN 
    If (a<c) and (e=a) THEN
        b := a;
ELSE
Without access to falgs, programming my code-generator becomes too difficult.
Please, add this instructions to spec.

Last edited by tronix286; July 5th, 2011 at 08:59..
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Old July 6th, 2011, 08:55   #567
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Quote:
Originally Posted by tykel View Post
Nice work, I'm impressed!

...How about a tech demo now?
I'll make a game for Chip16 for sure .
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Old July 9th, 2011, 02:49   #568
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I have a very tough problem, i thought i could solve it but looks like it's giving me a lot of trouble. It's about the opcode pointer and register identifiers (of all places, i know). The way i coded my chip-8 emulator is somewhat different to the way i learned in chip-16, i was hoping if maybe i could do the same for chip-16 in a similar fashion.

Here's an example of what i mean.

For instance in chip-8, i wrote the identifiers and fetcher this way:

Code:
addr = (OpCode And &HF000) >> 12 //XXXX 0000 0000 0000
vx = (OpCode And &HF00) >> 8 //0000 XXXX 0000 0000
vy = (OpCode And &HF0)  >> 4 //0000 0000 XXXX 0000
nibble = (OpCode And &HF) >> 0 //0000 0000 0000 XXXX
kk = (OpCode And &HFF)


'fetches opcode
OpCode = (RAM(PC) << 8 Or RAM(PC + 1))

Here's what i have so far, and i admit i still get confused despite how much i think i know about it.

Code:
Nibble = OpCode And &HF >> 24  //00 00 0X 00
HHLL = ??? //00 00 00 XX | 00 00 XX 00
RX = OpCode And &HF >> 16 //00 0X 00 00 
RY = OpCode and &HF0 >> 8 //00 X0 00 00 
RZ = Nibble //00 00 0X 00


'fetcher
OpCode = Ram(PC) Or (Ram(PC + 1) << 8) Or (Ram(PC + 2) << 16) Or (Ram(PC + 3) << 24)

This leads me to believe i still need plenty work when it comes to bit shifting, sorry i know this is a drag.
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Last edited by LoRd_SnOw; July 9th, 2011 at 03:20..
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Old July 9th, 2011, 03:50   #569
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Lord_Snow, this snippet from my emu should help:
Code:
#define _rx   ((op >>  8) & 0xf)
#define _ry   ((op >> 12) & 0xf)
#define _rz   ((op >> 16) & 0xf)
#define _hhll ((op >> 16) & 0xffff)

tbh its confusing because in the chip-16 doc the opcodes should've been written from MSB to LSB, but they're written in the reverse byte order.
i.e. this is how ADD is written:
42 YX 0Z 00

but it more easily to read written like this:
00 0Z YX 42

now its clear that to get the 'Y' register for example,
you first shift right by 12, which gives you:
00 00 00 ZY
then AND with 0xf, which gives you:
00 00 00 0Y
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Last edited by cottonvibes; July 9th, 2011 at 04:01..
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Old July 9th, 2011, 06:38   #570
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Thanks that explained a lot, i think i understand it a lot better now.

One other question. when you define the identifiers, does the opcode pointer still need to be at the very beginning with the register identifiers? it seems like when i comment out Opcode = ram(PC), all i ever seem to get is something like this:


Quote:
4 4 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
56 38 CLS 1 1
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
112 70 VBLNK 2 2
128 80 RET 21 15
4 4 CLS 1 1
4 4 CLS 1 1
4 4 CLS 1 1
4 4 CLS 1 1
56 38 CLS 1 1
I figured it needed to be removed since the fetcher already includes ram(pc).

However, when i don't comment Opcode = ram(pc) out, i get an exception overflow.

And when i do comment out the fetcher but leave the pointer, i get these opcodes in my logs followed by an exception overflow at opcode 0x14 for the GB c16 demo

Quote:
4 4 SPR HHLL 4 4
8 8 LDI RX, HHLL 32 20
12 C LDI RX, HHLL 32 20
16 10 LDI RX, HHLL 32 20
20 14 LDI RX, HHLL 32 20
24 18 LDI RX, HHLL 32 20
28 1C ADDI RX 64 40
32 20 BGC N 3 3
36 24 LDI RX, HHLL 32 20
40 28 CALL HHLL 20 14
0 0 CLS 1 1
4 4 SPR HHLL 4 4
8 8 LDI RX, HHLL 32 20
12 C LDI RX, HHLL 32 20
16 10 LDI RX, HHLL 32 20
20 14 LDI RX, HHLL 32 20
24 18 LDI RX, HHLL 32 20
28 1C ADDI RX 64 40
32 20 BGC N 3 3
36 24 LDI RX, HHLL 32 20
40 28 CALL HHLL 20 14
0 0 CLS 1 1
4 4 SPR HHLL 4 4
8 8 LDI RX, HHLL 32 20
I'm stomped, did i set up the fetcher correctly?
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Old July 11th, 2011, 17:33   #571
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CHip16 game: Ninja

Hello,

I come up with a new game for Chip16.
It's a test rom... But it doesn't test you emus. It tests your ninja's skills .

Have fun!!!
Attached Images
File Type: gif Screenshot - 11_07_2011 , 18_26_15.gif (4.9 KB, 21 views)
File Type: gif Screenshot - 11_07_2011 , 18_27_02.gif (4.9 KB, 27 views)
Attached Files
File Type: zip BC-Ninja.zip (13.3 KB, 15 views)
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Old July 11th, 2011, 22:05   #572
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Hey, nice job BestCoder, you showcase a number of features from other roms! Why not share the source?
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Old July 12th, 2011, 23:44   #573
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So far, only have the palette test working with this setup, any ideas why?

Code:
Do While (Cycle = 1)
            If Pause = 0 Then

                Nibble = CInt((OpCode >> 16) And &HF) '00 00 0X 00
                HHLL = CInt((OpCode >> 16) And &HFFFF) 'XX 00 00 00  | 00 XX 00  00
                RX = CInt((OpCode >> 8) And &HF) '00 00 0X 00
                RY = CInt((OpCode >> 12) And &HF) '00 00 X0 00
                RZ = Nibble 'CInt((OpCode >> 16) And &HF) '00 0X 00 00

                Select Case (OpCode And &HFF) ' 00 00 00 XX
                    Case &H0 '00 00 00 00    'NOP               Not operation. Wastes a cycle.
                        If BackgroundWorker1.WorkerReportsProgress = True Then
                            lbl_opcode.Text = (PC & " " & Hex(PC) & " " & "NOP" & " " & OpCode & " " & Hex(OpCode))
                        End If
End Select
                OpCode = Ram(PC) Or (Ram(PC + 1) << 8) Or (Ram(PC + 2) << 16) Or (Ram(PC + 3) << 24)
                System.Threading.Thread.Sleep(0)
pc =+ 4
loop
And should the select case(OpCode And &HFF) really be setup like this?
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Old July 13th, 2011, 07:00   #574
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@LoRd_SnOw

Have you used the test rom ? Maybe it could help you.

http://forums.ngemu.com/web-developm...ml#post1976103

Check also if the stack is initialised at the correct value.


@Tykel

Here are the sources. Feel free to ask questions if something isn't clear.
Attached Files
File Type: zip Ninja-Sources.zip (42.2 KB, 15 views)

Last edited by BestCoder; July 13th, 2011 at 07:12..
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Old July 13th, 2011, 19:34   #575
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does this game use the new spec?
it crashes on mschip16 :/
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Old July 13th, 2011, 19:38   #576
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Yes, It's using the new specs
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Old July 14th, 2011, 02:54   #577
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Quote:
Originally Posted by BestCoder View Post
@LoRd_SnOw

Have you used the test rom ? Maybe it could help you.

http://forums.ngemu.com/web-developm...ml#post1976103

Check also if the stack is initialised at the correct value.


@Tykel

Here are the sources. Feel free to ask questions if something isn't clear.
Hey, yes i did try it but it won't even display anything on screen with this kind of configuration. However, with the standard that mostly everyone has followed, it works just fine. I'm only trying to do this to learn, but i think I've just about given up... I was hoping that anyone here might know more about this problem that i'm having but i guess not. :/

Although i did have a crazy idea on how to get it working, I was thinking if maybe the switch needed to be re-organized in a certain way, much like how chip-8 was designed. But that would take a very confusing and long time and theres no guarantee that i would get it right or if even needs to be setup that way. ><

... heh at this rate, i won't be making any c16 games any time soon.
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Old July 14th, 2011, 06:45   #578
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I've tried using you configuration and it's working fine.

LL=(opcode&0x00FF0000)>>16;
HH=(opcode&0xFF000000)>>24;
HHLL =((opcode >> 16) & 0xFFFF);
X = ((opcode >> 8) & 0xF);
Y = ((opcode >> 12) & 0xF);
Z = ((opcode >> 16) & 0xF);
bits=(opcode&0xFF);

I've noticed that you didn't get the HH and LL bits. How do you manage with opcodes using them?
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Old July 14th, 2011, 17:39   #579
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With the previous format, i simply pointed HHLL into my declarations.

much like this:

Code:
                        SPR_WH = HHLL
On a side note, i didn't even know i needed to do this for HHLL:

Code:
LL=(opcode&0x00FF0000)>>16;
HH=(opcode&0xFF000000)>>24;
I figured it was the samething as this:

Code:
HHLL = CInt((OpCode >> 16) And &HFFFF)
I just tried your implementation, it doesn't seem to work either, I can't see what i'm doing wrong.

Perhaps you could have a look at my source in order to identify what my problem is?
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Old July 14th, 2011, 18:12   #580
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Where can I find the sources ?
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